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STL80N4LLF3
N-channel 40V - 0.0042 - 80A - PowerFLATTM (6x5) STripFETTM Power MOSFET for DC-DC conversion
General features
Type STL80N4LLF3 VDSS 40V RDS(on) <0.005 ID 20A (1)
1. When mounted on FR-4 board of 1 inch , 2oz Cu, t<10 sec
Improved die-to-footprint ratio Very low profile package (1mm Max) Very low thermal resistance Conduction losses reduced Switching losses reduced
PowerFLATTM( 6x5 )
Description
This series of product utilizes the latest advanced design rules of ST's proprietary STripFETTM Technology. The resulting Transistor is optimized for low on-Resistance and minimal gate charge. The chip-scaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STL80N4LLF3 Marking L80N4LLF3 Package PowerFLATTM (6x5) Packaging Tape & reel
November 2006
Rev 7
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Contents
STL80N4LLF3
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5
Test circuit
................................................ 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STL80N4LLF3
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS VGS
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate- source voltage Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (continuous) at TC = 25C Drain current (pulsed) Total dissipation at TC = 25C Total dissipation at TC = 25C Derating factor
(3)
Value 40 16 18 80 50 20 80 80 4 0.03 -55 to 150
Unit V V V A A A A W W W/C C
ID (2) ID ID
(2) (3) (4)
IDM
PTOT (2) PTOT(3)
Tstg Tj
Storage temperature Operating junction temperature
1. Guaranteed for test time < 15ms 2. The value is rated according Rthj-c 3. When mounted on FR-4 board of 1 inch , 2oz Cu, t < 10 sec 4. Pulse width limited by safe operating area
Table 2.
Symbol Rthj-c Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case max Thermal operating junction-pcb max Value 1.56 31.2 Unit C/W C/W
1. When mounted on FR-4 board of 1 inch , 2oz Cu, t<10 sec
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Electrical characteristics
STL80N4LLF3
2
Electrical characteristics
(TCASE = 25C unless otherwise specified) Table 3.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS = 0 VDS = Max rating VDS = Max rating@125 C VGS = 16V VDS = VGS, ID = 250 A VGS = 10V, ID = 10 A VGS = 4.5V, ID =10 A 1 0.0042 0.005 0.005 0.007 Min. 40 10 100 200 Typ. Max. Unit V A A nA V
Table 4.
Symbol Ciss Coss Crss
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Gate input resistance Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 2530 574 29 Max. Unit pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0 f=1 MHz Gate DC Bias = 0 Test signal level = 20mV open drain VDD = 32V, ID = 20 A, VGS = 4.5V (see Figure 13)
RG Qg Qgs Qgd
1
3 21.5 6.9 8.2
5 28
nC nC nC
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STL80N4LLF3
Electrical characteristics
Table 5.
Symbol td(on) tr td(off) tr
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 20V, ID = 10A, RG= 4.7 VGS = 10V (see Figure 15) Min Typ 17 25 62 9 Max Unit ns ns ns ns
Table 6.
Symbol ISD ISDM
(1)
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 20 A, VGS = 0 ISD = 20A,VDD = 20V di/dt = 100A/s Tj = 150C(see Figure 14) 43 64 3 Test conditions Min Typ. Max 20 80 1.2 Unit A A V ns nC A
VSD(2) trr Qrr IRRM
1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300s, duty cycle 1.5%
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Electrical characteristics
STL80N4LLF3
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Normalized BVDSS vs temperature
Figure 6.
Static drain-source on resistance
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STL80N4LLF3 Figure 7. Gate charge vs gate-source voltage Figure 8.
Electrical characteristics Capacitance variations
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
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Test circuit
STL80N4LLF3
3
Test circuit
Figure 13. Gate charge test circuit
Figure 12. Switching times test circuit for resistive load
Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit
Figure 16. Unclamped inductive waveform
Figure 17. Switching time waveform
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STL80N4LLF3
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STL80N4LLF3
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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STL80N4LLF3
Revision history
5
Revision history
Table 7.
Date 13-May-2005 20-Jun-2005 22-Jun-2005 04-Jan-2006 06-Jun-2006 04-Sep-2006 22-Nov-2006
Revision history
Revision 1 2 3 4 5 6 7 First release. Updated mechanical data New RG value on Table 6 New footprint Complete version New template, no content change Corrected part number Changes
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STL80N4LLF3
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